The present invention relates to a means for improving the performance in a pipeline microprocessor and in particular wherein the microprocessor deals with conditional branch microinstructions.
In previous hardwired computers, selection of control signals required for executing each instruction, of an instruction set, stored in the computer main memory was fixed by the design of decoders and encoders within the computer. With microprocessing, however, a separate control store memory (COS) stores a set of microinstructions (a microprogram) for executing each of the instructions in main memory (called a macroinstruction), and each microinstruction comprises a plurality of bits. Each bit position within a microinstruction can be used to generate directly a control signal. However, most microprocessors use coded fields of bits which transmit bit signals to a decoder and the output signals from the decoder generate the control signals.
A complete cycle of a microprocessor generally comprises the fetching of a microinstruction and the execution thereof. In the prior art, to minimize the cycle time and speed up the processing in the microprocessor, designs of microprocessors have included the overlapping of fetch and execution operations.
This is accomplished in the prior art by providing a pipeline register between the COS and the instruction execution unit of the microprocessor. Such an arrangement allows the microprocessor to fetch the next required microinstruction and get it ready in the COS while a current microinstruction, stored in the pipeline register, is being executed.
However, even in a pipeline register design, a problem occurs if the results of the execution of the current microinstruction are required to determine the address of the next microinstruction. For example, where the microprogram includes conditional jump or branch microinstructions, it has been necessary to wait until a condition specified in the conditional microinstruction becomes valid in order that the condition might be tested. If the test result is true then the next address (from which the next microinstruction is brought) is determined from information in the current microinstruction. On the other hand if the test result is false the next address activated will be determined by incrementing the address of the current instruction.
Typically, the COS is of the random-access-memory (RAM) type. The access time of a particular microinstruction at a selected address within the COS is quite often a large percentage of the overall cycle time of the microprocessor. Therefore, it would be desirable to begin fetching a microinstruction before the execution of the current microinstruction in the pipeline register is completed. As mentioned above in the prior art it has been necessary to wait until the condition of the microprocessor is tested before determining whether or not the jump address, identified in a conditional jump microinstruction, is to be employed. Accordingly it has not been the practice to access the next microinstruction in the RAM (since the test results must first be determined) before the end of the microprocessor cycle. In the prior art, even in a pipeline register approach, problems arise in trying to overlap the fetch and execution of microinstructions when the current microinstruction being executed is a conditional jump microinstruction.
U.S. Pat. No. 3,418,638, issued to D. W. Anderson et al, relates to devices in a data processing machine for prefetching and predecoding of succeeding instructions to enable implementation of a "branch on condition subsequent instruction" at the highest possible speed, and with a minimum of delay in data processing.
The Anderson et al patent discloses a loop mode which is a condition of the instruction set unit (labeled I box in the patent). The I box is in a loop mode whenever the instructions stacked in a buffer (Buffer 156 in the patent) contain the entire loop. The system described in the patent is designed so that, if the I box is in loop mode, the system assumes that a conditional branch will be required. If the I box is not in loop mode then the system assumes that the next sequential instruction should be fetched and executed. In this Anderson et al patent description the program path for conditional branch instructions is determined by the hardware. The loop mode disclosed in this patent can not provide for random branching on conditional branch instructions located in a COS.